Data converters are commonly used devices to interface between the physical world and the computer world. Analog-to-digital converters (ADC) translate an analog signal into a corresponding digital representation while digital-to-analog converters (DAC) perform the reverse operation. There are numerous categories of ADCs, including (among others) flash, delta-sigma, dual-slope integration and successive approximation register ADCs. The present invention will be described in the context of an ADC and, in particular, will be described in the context of a successive approximation register (SAR) ADC. However, the present invention is not in any way limited to being used in a SAR ADC and may be used in any suitable data converter.
As illustrated in FIG. 1, in a prior art SAR ADC 100, an analog input voltage from an analog signal is held in a sample/hold circuit 102 and input to a comparator 104. Under the direction of SAR control logic 106, an N-bit register 108 is initialized to midscale (with the most significant bit set to 1 and all other bits set to 0). The register output is converted to an analog value VDAC in an N-bit D/A converter (DAC) 110; analog value VDAC will thus equal ½ the reference voltage VREF provided to the D/A converter 110. Analog value VDAC is coupled to the other input of the comparator 104 and compared with the analog input voltage. If the analog input voltage is greater than analog value VDAC, the output of the comparator 104 is a 1 and the most significant bit of the register remains a 1. If the analog input voltage is less than analog value VDAC, the output of the comparator 104 is a 0 and the most significant bit of the register is set to 0. The SAR control logic 106 then sets the next most significant bit of the register 108 to 1 and another comparison is performed. The process is continued until a comparison has been performed with the least significant bit of the register 108 set to 1. At completion, an N-bit digital representation of the analog input voltage is stored in the register 108 and may be output serially or in parallel.
FIG. 2 is a plot of the transfer characteristics of an ideal ADC in which, as the analog input voltage increases, the digital output code increments with a step width of the value of one least significant bit (LSB). Typically, the output is less than ideal due to any of several types of errors, such as (among others) offset errors, gain errors, integral nonlinearity errors and differential nonlinearity (DNL) errors.
One common configuration of the DAC inside an SAR ADC includes a resistive ladder network which creates binary weighted currents. Another configuration includes a capacitive ladder network with weighted values employing charge redistribution to generate the analog output voltage. The operation of the charge redistribution DAC (CRDAC) is well known. However, the linearity of an SAR ADC is at least partially dependent upon the linearity of the internal DAC and, when a CRDAC is used, slight variations in capacitor values may contribute to nonlinearities. Even after the capacitors have been trimmed and calibrated, such factors as aging and fluctuations in temperature or reference voltage may still cause linearity errors. FIG. 3 is a plot of the transfer characteristics of an ADC with DNL errors, as indicated by some step widths greater than or less than 1 LSB.
Various techniques have been developed to address the issue of differential nonlinearity. Some involve lookup tables utilized to correct the DAC output by adding/subtracting correction values. Others involve regular recalibration of the DAC capacitors.
Consequently, a need remains for reducing differential nonlinearities in data converters such as successive approximation analog-to-digital converters.